Field of the Invention
The invention relates to a method for selective filtering with a coefficient and filter calculation unit, a phase detector, a loop filter, and a digital oscillator, these units simulating different selective filters depending on coefficients used for the filter calculation.
Systems for receiving digital data generally require a device for recovering the data clock signal implicitly contained in the signal. In principle, there are two approaches for receiving the data: (1) the clock control loop contains the circuit that supplies the sampling clock of the analog/digital converter (“ADC”) (e.g. VCXO), and (2) the clock signal of the ADC is asynchronous with respect to the data clock. A fully digital control circuit calculates by interpolation from the output values of the ADC samples in a timing pattern that is synchronous with the data clock. There exist prior art circuits that achieve the task in baseband. Most applications have filters upstream or downstream of the ADC, which filters select the signal that is intended to be processed, i.e., suppress adjacent signals and other interference signals. These filters are generally optimized for a fixed bandwidth or data rate, such as, e.g., surface acoustic wave filters. Stringent requirements regarding phase linearity are usually imposed on the filter so that the pulse shape of the data signals is not distorted.
Basic theories with regard to fully digital clock recovery in digital modems by interpolation are discussed in an article by Floyd M. Gardener titled “Interpolation in Digital-Modems —Part I: Fundamentals”. The article appeared in the journal IEEE Transactions on Communications, Vol. 41, No. 3, in March 1993.
A further approach in the prior art uses analog filters having a controllable bandwidth upstream of the ADC. However, these filters are expensive and, particularly in CMOS technology, are difficult to integrate on a circuit. Analog filters fundamentally have phase distortions that have to be reduced using additional circuits. Moreover, the sampling frequency of the ADC has to be adapted to the signal bandwidth.
Another approach lies in providing a multistage digital selection filter upstream of the clock recovery and in carrying out the fine adjustment of the sampling frequency by interpolation again. After each stage of the filter, the sampling rate is reduced by a fixed factor. The approach has a disadvantage in that many filter stages are required for small bandwidths. Thus, the filter becomes complicated. Moreover, a fixed gradation means that not all the interference components can be suppressed, which generally leads to an increase in outlay in the downstream interpolator.
Lambrette U et al.: “VARIABLE SAMPLE RATE DIGITAL FEEDBACK AND TIMING SYNCHRONIZATION” in I.E.E.E. Vehicular Technology Conference, New York, USA, I.E.E.E., Rd. Conf. 47, pages 1348-1352, discusses two algorithms for digital receivers for processing a broader range of different sampling rates. One of the algorithms is also based on filtering the received signals prior to the time synchronization. A time synchronization algorithm is presented that is not data-aided, is based on digital feedback, and can process symbol rates deviating from a sampling rate.
The paper by D. Kim et al.: “DESIGN OF OPTIMAL INTERPOLATION FILTER FOR SYMBOL TIMING RECOVERY” in I.E.E.E. Transactions on Communications. I.E.E.E. Inc., New York, USA, Vol. 45, No. 7, pages 877-884, discloses an optimized interpolation filter for recovering the symbol timing in a digital receiver, in which the sampling rate of the analog-to-digital converter on the input side is not synchronized with the symbol clock of the transmitter.
The paper by K. Bucket et al. “PERIODIC TIMING ERROR COMPONENTS IN FEEDBACK SYNCHRONIZERS OPERATING ON NONSYNCHRONIZED SIGNAL SAMPLES” I.E.E.E. Transactions on Communications, I.E.E.E. Inc., New York, USA, Vol. 46, No. 6, pages 747-749, reveals that the synchronization error contains periodic components through a loop for timing recovery on detection of nonsynchronized samples of a noisy sine signal. These periodic errors are produced exclusively by non-ideal interpolation between the nonsynchronized signal samples and disappear when synchronized sampling is performed.